1. Field of the Invention
This invention relates in general to semiconductor circuits and in particular to forming a strained semiconductor layer.
2. Description of the Related Art
For some applications, it is desirable to produce a layer of strained silicon over an insulator such as with a semiconductor on insulator (SOI) configuration. A strained silicon layer is a layer of silicon whose lattice spacing are different than a lattice spacing (e.g. 5.43095 A) of natural silicon (e.g. relaxed silicon crystal). One example of a strained silicon spacing is 5.4843 A for 1% tensile strain. A strained silicon layer may provide for a greater mobility of electrons and holes than a layer of relaxed silicon crystal.
One method of forming a strained silicon layer is to form a layer of silicon on a template layer having a lattice spacing larger than that of natural silicon crystal. The resultant silicon formed (e.g. by expitaxial deposition) on top of the template layer is stressed to provide a larger or smaller lattice spacing.
FIG. 1 shows a prior art wafer 101 in an example of a SOI substrate configuration that includes a silicon germanium (SiGe) layer 103 located on an insulating layer 105 (e.g. silicon dioxide). Insulating layer 105 is located on layer 107.
Referring to FIG. 2, to increase the content of germanium in a template layer and thereby increase its lattice spacing, layer 103 is subject to an oxidation process to enrich the amount of germanium in the bottom portion 205 of layer 103. The top portion is oxidized to form SiO2 layer 203. During the oxidation process, germanium atoms from the top portion of layer 103 are injected into portion 205 and diffuse throughout 205. In one example, the oxidation process involves heating wafer 101 as high as 1200 C in an atmosphere containing oxygen gas with an inert gas (e.g. Argon or N2) as a dilutant.
The resulting SiO2 layer 203 is then removed (e.g. by etching). A layer of silicon is then grown (e.g. epitaxially) on layer 205. Because layer 205 has a larger lattice spacing, the top silicon layer will be under tensile biaxial stress to provide a larger lattice spacing than with naturally occurring silicon crystal.
One problem with this process is that template layer 205 is not fully relaxed in that the lattice spacing does not fully correspond to a crystal having the percentage of germanium that layer 205 has. Accordingly, not all injected germanium atoms are on lattice sites, the layer is stressed by the underlying insulating layer 105, and the interstitial germanium and silicon atoms of layer 205 are prone to form defects.
Another problem that may occur with such a process is that the germanium may not adequately diffuse to the remaining portion of the silicon germanium layer. Accordingly, there may be a relatively high concentration of germanium at the top portion of the remaining layer as opposed to the germanium concentration of the lower portion of the remaining layer. These differences in germanium concentration in the template layer may cause dislocations which could lead to a dysfunctional semiconductor device formed in the area of the dislocations.
FIG. 3 shows a two dimensional view of a lattice 301 of silicon germanium crystal having smaller lattice spacing than a relaxed silicon germanium crystal having the same germanium content. Interstitial germanium atoms (e.g. 305) and interstitial silicon atoms (e.g. 311) are shown in FIG. 3 located between lattice sites (e.g. 313 and 315). These interstitial atoms may cause extended defects in the silicon germanium template layer and in a subsequently formed strained silicon layer.
What is needed is an improved method for forming a template layer.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.